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evaluation board for dual, interleaved, step-down dc-to-dc controller with tracking eval-adp1829 rev. 0 evaluation boards are only intended for device evaluation and not for production purposes. evaluation boards are supplied as is and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. no license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. analog devices reserves the right to change devices or specifications at any time without notice. trademarks and registered trademarks are the property of their respective owners. evaluation boards are not authorized to be used in life support devices or systems. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. introduction this data sheet describes the design, operation, and test results obtained with the adp1829 evaluation board. the input range for this evaluation board is 5.5 v to 18 v. the output voltages are configured for v out1 = 1.8 v (with a maximum current limit of 15 a) and for v out2 = 1.2 v (with a maximum current limit of 15 a). all of the results tested on the evaluation board ran at a switching frequency (f sw ) of 300 khz with v in = 12 v, v out1 = 1.2 v at up to 15 a, and v out2 = 1.8 v at up to 15 a. general description adp1829 is a versatile, dual output, interleaved, synchronous pwm buck controller that generates two independent outputs from an input voltage of 2.9 v to 18 v. it is ideal for a wide range of high power applications, such as dsp and processor core, general-purpose power in telecommunications, medical imaging, pc gaming, and industrial applications. each channel can be configured to provide output voltage from 0.6 v to 85% of the input voltage. the two channels operate 180 out of phase, which reduces the current stress on the input capacitor and allows the use of a smaller and lower cost input capacitor. the adp1829 operates at a pin selectable fixed switching frequency of either 300 khz or 600 khz. for some noise sensitive applications, it can also be synchronized to an external clock to achieve switching frequency between 300 khz and 1 mhz. the adp1829 includes an adjustable soft start to limit input inrush current, voltage tracking for sequencing or ddr termination, independent power good output, and a power enable pin. it also provides current-limit and short-circuit protection by sensing the voltage on the synchronous mosfet. the adp1829 evaluation board schematic is shown in figure 16 . the switching frequency chosen is 300 khz to provide good efficiency over a wide range of input and output conditions. table 2 is the bill of materials (bom) for the evaluation board. 06808-020 figure 1. digital picture of the adp1829 evaluation board
eval-adp1829 rev. 0 | page 2 of 16 table of contents introduction ...................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 component design .......................................................................... 3 input capacitor............................................................................. 3 inductor selection ........................................................................ 3 output capacitor selection......................................................... 3 mosfet selection....................................................................... 4 soft start ........................................................................................ 4 current limit ................................................................................ 4 voltage tracking............................................................................5 compensation design ..................................................................5 test results .........................................................................................7 pcb layout guidelines.....................................................................9 evaluation board schematic and layout .................................... 11 ordering information.................................................................... 13 bill of materials........................................................................... 13 ordering guide .......................................................................... 14 esd caution................................................................................ 14 revision history 7/07revision 0: initial version
eval-adp1829 rev. 0 | page 3 of 16 component design input capacitor the input capacitor carries the input ripple current, allowing the input power source to supply only the dc current. select the input bulk capacitor based on its ripple current rating. the two channels in the adp1829 operate 180 out of phase, thus reducing the current rating on the input capacitor. if the maximum output load currents are about the same, the input ripple current for both channel 1 and channel 2 is less than half of the higher of the output load currents. the input capacitor current is approximated as 2 l ripple i iin (1) where i l is the current though the inductor. if the load currents of the two channels are significantly different (the smaller is less than 50% of the larger), in this case, if the duty cycle d is between 20% and 80%, the input capacitor ripple current is approximately i l d(1 ? d). if duty cycle d is less than 20% or greater than 80%, the ripple current is approximately 0.4i l . inductor selection the choice of inductance determines the ripple current in the inductor. less inductance leads to more ripple current, which increases the output voltage ripple and conduction losses in the mosfets, but allows using smaller inductors and less output capacitance for a specified peak-to-peak voltage overshoot at load transient. generally, choose an inductor value such that the inductor ripple current is approximately 1/3 of the maximum dc output current. use the following equation to calculate the inductor value: sw l ut o fi dv l ? = )1( (2) where: l is the inductor value. f sw is the switching frequency. v out is the output voltage. d is the duty cycle. i l is the inductor ripple current, typically 1/3 of the dc load. output capacitor selection choose the output capacitor to set the desired output voltage ripple. the output voltage ripple is a function of the inductor ripple current and the capacitor impedance at the switching frequency. the output voltage ripple can be approximated as ? ? ? ? ? ? ? ? += out sw l out cf esriv 8 1 (3) for high esr capacitors, the ripple is dominated by the esr, while for low esr capacitors, the output ripple is dominated by the capacitor. esl of the capacitor also affects the output ripple, especially the though-hole electrolytic capacitors. in practical designs, multiple types of capacitors are used. for instance, a mlcc (multilayer ceramic capacitor) can be paralleled with an electrolytic capacitor to reduce the esl and esr. another factor that should be considered is the load-step transient response on the output, where the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. a minimum capacitance at the output is needed in order to have a fast load-step response and reasonable overshoot voltage. the minimum capacitance can be calculated as up ut o out vv li c = 2 2 min1out, (4) down uto in out vvv li c ? = )(2 2 min2out, (5) where: i o is the step load. v up is the output voltage overshoot when the load is stepped down. v down is the output voltage overshoot when the load is stepped up. v in is the input voltage. c out,min1 is the minimum capacitance according to the overshoot voltage v up . c out,min2 is the minimum capacitance according to the overshoot voltage v down . select an output capacitance that is greater than both c out, min1 and c out, min2 . make sure that the ripple current rating of the output capacitors is greater than the following current: 12 2 l cout i i = (6)
eval-adp1829 rev. 0 | page 4 of 16 mosfet selection the choice of mosfet directly affects the dc-to-dc converter performance. the mosfet must have low on resistance (r dson ) to reduce the conduction loss, and low gate charge to reduce switching loss. for the low-side (synchronous) mosfet, the dominant loss is the conduction loss. it can be calculated as dson l uto lowc r i id p ? ? ? ? ? ? + ?= 12 )1( 2 2 . (7) the gate charge loss is dissipated by the adp1829 regulator and gate drivers. the gate charge loss is approximated by the follow- ing equation: swggg fqvp = (8) where: v g is the driver voltage. q g is the mosfet total gate charge. the high-side (main) mosfet has to be able to handle two main power dissipations: conduction loss and switching loss. the switching loss is related to rise and fall times of the mofset, the switching frequency, the inductor current, and the input voltage. the high-side mosfet switching loss is approximated by the equation 2 )( sw frlin t fttiv p + = (9) where t r and t f are the rise and fall times of the mosfet. they can be calculated by g spg gd gs r r vv q q t ? + = 2 and g sp gd gs f r v q q t + = 2 where: q gs and q gd are the parameters of mosfet, provided from the mosfet data sheet. r g is the resistor on the driver. v sp is approximated using m t u o th sp g i vv + where g m is the mosfet transconductance. the high-side mosfet conduction loss can be calculated as dson l ut o highc r i idp ? ? ? ? ? ? += 12 2 2 , (10) it is important to choose a high-side mosfet that balances the conduction loss and the switching loss. make sure that the selection mosfet can meet the total power dissipation when combining the switching and conduction loss (generally about 1.5 w for a single d-pak, 0.8 w for an so-8, and 1.2 w for a powerpak-so8). soft start the adp1829 uses an adjustable soft start to limit the output voltage ramp-up period, thus limiting the input inrush current. the soft start is set by selecting the capacitor, c ss , from ss1 and ss2 to gnd. the adp1829 charges c ss to 0.8 v through an internal 90 k resistor. the voltage on the soft-start capacitor while it is charging is ? ? ? ? ? ? ? ? ?= ? ss ss rc t css e v 18.0 the soft start period ends when the voltage on the soft-start pin reaches 0.6 v. ? ? ? ? ? ? ?? = 8.0 6.0 1ln r t c ss ss where r = 90 k and t ss is the soft-start time. therefore, f10015.8 6 ? = ss ss t c (11) current limit the adp1829 employs a unique, programmable cycle-by-cycle lossless current-limit circuit. in every switching cycle, the voltage drop across the synchronous mosfet r dson is measured to determine if the current is too high. this measurement is done by an internal comparator and an external resistor. the csl1 and csl2 pins are the inverting inputs of the current-limit comparators and the noninverting inputs are referenced to pgnd1 and pgnd2, respectively. a resistor is tied between the csl pin and the switch node, which is the drain of the synchronous mosfet. a 50 a current is forced though the resistor to set an offset voltage drop across it. when the synchronous mosfet is on and the voltage drop on it exceeds the offset voltage on the external resistor, an overcurrent fault is flagged. when the adp1829 senses an overcurrent condition, the next switching cycle is suppressed, and the soft-start capacitor is discharged. the adp1829 remains in this mode as long as the overcurrent condition persists. when the overcurrent condition is removed, operation resumes in soft-start mode.
eval-adp1829 rev. 0 | page 5 of 16 the external current-limit resistor can be calculated by the following equation: a r i i r dson l cls ? ? ? ? ? ? + = 50 2 limit (12) where i limit is the limit current. voltage tracking the adp1829 features tracking inputs, trk1 and trk2, which make the output voltage track another voltage. this is especially useful in core and i/o voltage sequencing applications. the adp1829 tracking input is an additional positive input to the error amplifier. the feedback voltage is regulated to the lower of the 0.6 v reference or the voltage at trk, so a lower voltage on trk limits the output voltage. this feature allows implementation of two different types of tracking: coincident tracking, where the output voltage is the same as the master voltage until the master voltage reaches regulation, or ratio- metric tracking, where the output voltage is limited to a fraction of the master voltage. in all tracking configurations, the master voltage should be higher than the slave voltage. note that the soft-start time of the master voltage should be set to be longer than the soft start of the slave voltage. that forces the rise time of the master voltage to be imposed on the slave voltage. if the soft start of the slave voltage is longer, the slave comes up more slowly and the tracking relationship is not seen at the output. the slave channel should still have a soft-start capacitor to give a small but reasonable soft-start time to protect in case of restart after a current-limit event. for more information about the voltage tracking, see the adp1829 data sheet. compensation design figure 2 shows the voltage mode control loop for a synchronous buck converter. usually, design the compensator to get adequate phase margin and high cross frequency for stable operation and good transient response. there are two types of compensation circuits for the adp1829 , type ii and type iii. for more details, see the adp1829 data sheet. v in l r pwm comparator c esr error amp z 1 z 2 reference comparator 06808-002 figure 2. voltage mode buck converter reference comp c2 c1 c 3 r4 r2 r1 r3 v o 06808-003 figure 3. type iii compensation circuit the buck converter control to ou tput transfer function can be described by the following equation: 2 2 )2(2 1 2 1 1 1 )( )( )( o o z in o vd f s fq s f s r v sd sv sg + + + + == (13) where: cr f c z = 2 1 lc rr r f c o + = 2 o c fcrrl r q + + = 2 1 1 r c is the esr of the output capacitor.
eval-adp1829 rev. 0 | page 6 of 16 the compensation network consists of the error amplifier and the impedance networks z1 and z2. figure 3 shows a type iii compensation circuit. it provides two poles and two zeros. the transfer function of this compensator is ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + ? = p2 1p z2 z1 2 1 2 1 2 2 1 2 1 )( f s f s f f s s a sg ea ea (14) where: 221 )( 1 rcc a ea + = 24 2 1 cr f z1 = 332 z2 )(2 1 crr f + = 33 2 1 cr f 1p = 21 21 4 p2 2 1 cc cc r f + = the loop gain can be written as ramp ea vd v sgsg st )()( )( = (15) where v ramp is the pwm ramp peak voltage; in the adp1829 , v ramp = 1.3 v. use the following guidelines to select the compensation components: 1. set the loop gain cross frequency f c . a good choice is to place the cross frequency f c at f s /10 for fast response. 2. cancel esr zero f z by compensator pole f p1 . 3. place the high frequency pole f p2 to achieve maximum attenuation of switching ripple and high frequency noise. a good choice is f p2 = (5 ~ 10) f c . 4. place two compensator zeros near the power stage resonant frequency f o . in general, place f z1 below f o and place f z2 between f o and f c . 5. check the phase margin to obtain good regulation performance.
eval-adp1829 rev. 0 | page 7 of 16 test results ch1 20.0mv b w ch2 5.00v m2.00s a ch2 5.90v t 53.60% 1 2 t 06808-004 figure 4. output ri pple of channel 1, v out = 1.8 v, f sw = 300 khz, channel 1: v out1 , channel 2: sw1 95 50 55 60 65 70 75 80 85 90 12345678910111213141516 efficiency (%) i o (a) 06808-006 figure 5. efficiency vs. load current, v out = 1.8 v, f sw = 300 khz ch1 10.0v b w ch2 5.00v m10.0ms a ch2 2.70v 1 2 3 4 t ch3 1.00v b w ch4 1.00v t 32.80% 06808-008 figure 6. soft start of channel 1, channel 1: en1, channel 2: pg1, channel 3: ss1, channel 4: v out1 ch1 20.0mv b w ch2 5.00v m2.00s a ch2 5.90v t 67.40% 1 2 t 06808-005 figure 7. output ri pple of channel 2, v out = 1.2 v, f sw = 300 khz, channel 1: v out2 , channel 2: sw2 90 50 55 60 65 70 75 80 85 12345678910111213141516 efficiency (%) i o (a) 06808-007 figure 8. efficiency vs. load current, v out = 1.2 v, f sw = 300 khz ch1 10.0v ch2 5.00v m10.0ms a ch2 2.70v 1 2 3 4 t ch3 1.00v ch4 1.00v t 34.40% 06808-009 figure 9. soft start of channel 2, channel 1: en2, channel 2: pg2, channel 3: ss2, channel 4: v out2
eval-adp1829 rev. 0 | page 8 of 16 ch1 10.0v ch2 5.00v m4.00ms a ch2 2.70v 1 2 3 4 t ch3 1.00v ch4 1.00v b w t 52.20% 06808-010 figure 10. disable channel 1, channel 1: en1, channel 2: pg1, channel 3: ss1, channel 4: v out1 ch1 50.0mv m400s a ch3 9.60a 1 3 t ch3 5.00a ? b w t 76.80% 06808-012 figure 11. load transient response of channel 1, 5 a to 15 a , v in = 12 v, v out = 1.8 v 1 2 3 4 t ch1 10.0v b w ch2 5.00v m4.00ms a ch4 2.80v ch3 1.00v b w ch4 1.00v t 32.80% 06808-014 figure 12. start into precharged channel 1, channel 1: v in , channel 2: low-side gate, channel 3: v out , channel 4: pok ch1 10.0v ch2 5.00v m10.0ms a ch2 2.70v 1 2 3 4 t ch3 1.00v b w ch4 1.00v t 56.80% 06808-011 figure 13. disable channel 2, channel 1: en2, channel 2: pg2, channel 3: ss2, channel 4: v out2 ch1 50.0mv m400s a ch3 9.60a 1 3 t ch3 5.00a ? b w t 76.80% 06808-013 figure 14. load transient response of channel 2, 5 a to 15 a, v in = 12 v, v out = 1.2 v 1 2 3 4 t ch1 10.0v b w ch2 5.00v m4.00ms a ch4 2.80v ch3 1.00v b w ch4 5.00v t 25.80% 06808-015 figure 15. start into precharged channel 2 channel 1: v in , channel 2: low-side gate, channel 3: v out , channel 4: pok
eval-adp1829 rev. 0 | page 9 of 16 pcb layout guidelines in any switching converter, some circuit paths carry high di/dt, which can create spikes and noise. other circuit paths are sensitive to noise. still others carry high dc current and can produce significant ir voltage drops. the key to proper pcb layout of a switching converter is to identify these critical paths and arrange the components and copper area accordingly. the following is a list of recommended layout practices for adp1829 , arranged in approximately decreasing order of importance: 1. keep the high current loops small. while the inductor is considered to have continuous high current, this current is switched alternately through the top and bottom fets. the current waveform in each fet is a pulse with very high di/dt, so the path to, through, and from each individual fet should be as short as possible. in designs that use a pair of d-pak or so-8 fets on one side of the pcb, it is best to counter-rotate the two so that the switch node is on one side of the pair and the high-side drain can be bypassed to the low-side source with a suitable ceramic bypass capacitor, placed as close as possible to the fets. this minimizes inductance around this loop through the fets and capacitor. in designs that place the two fets on opposite sides of the board, it may work well to place one fet directly opposite to (above and below) the other to form a minimal current loop area. again, make sure that the high-side drain is bypassed to the low-side source with a suitable ceramic bypass capacitor, connected as closely as possible to the fets to minimize the loop area. recommended ceramic capacitor values range from 4.7 f to 22 f depending upon the output current. this bypass capacitor is usually connected to a larger value bulk filter capacitor. 2. gnd, in bypass, v reg bypass, soft-start capacitors, and the bottom ends of the output feedback divider resistors should be tied to an (almost isolated) small ground plane under the ic. no high current or high di/dt signals should be connected to this ground plane. one via should connect gnd to the die paddle heat sink area. the agnd and pgnd planes should be separated before joining them together. other low current signal grounds can also be connected here if a ground connection is needed; these may include sync, freq, or ldosd. this ground area should be connected through one wide trace to the negative terminal of the output filter capacitors. because the adp1829 is a dual output controller, it is desirable to place the output filters of the two output voltages adjacent to each other. this provides the best accuracy for the two outputs. 3. pgnd pins handle high di/dt gate drive current returning from the source of the low-side mosfet. the voltage at this pin also establishes the 0 v reference for the ocp function and the csl pins. a small pgnd plane should connect the pgnd pins and the pv bypass capacitors through a wide and direct path to the source of the appropriate low-side mosfet. 4. gate drive traces (dh and dl) handle high di/dt so they tend to produce noise and ringing. they should be as short and direct as possible. if the overall pcb layout is less than optimal, slowing down the gate drive slightly can be very helpful to reduce noise and ringing. for this reason, it is occasionally helpful to place small value resistors (such as 10 ) in series with the gate traces. these can be populated with 0 if resistance is not needed. 5. the switch node is the interconnection of the source of the high-side fet with the drain of the low-side fet and the inductor. this is the noisiest place in the switcher circuit with large ac and dc voltage and current. this node should be wide to keep resistive voltage drop down. however, to minimize the generation of capacitively coupled noise, the total area should be small. the best layout generally places the fets and inductor all close together on a small copper plane to minimize series resistance and keep the copper area small. connect a direct and moderately sized trace from the switch node back to the sw pin and the csl resistor. this trace handles the high di/dt gate current for the high-side fet. the voltage on this trace is also sensed through the csl resistors and pins to sense an overcurrent condition. the high di/dt and sensing overcurrent do not occur at the same time. keep the compensation and feedback components away from the switch nodes and their associated components.
eval-adp1829 rev. 0 | page 10 of 16 6. the negative terminal of the output filter capacitors should be tied closely to the source of the low-side fet. doing this helps to minimize voltage differences between gnd and pgnd at the adp1829 . the current in these capacitors is not very high in a buck converter, but the output trace handles the full output current of the converter. high dc current flows through this trace to the input filter capa- citors, so it is generally helpful to place a bulk input filter capacitor close to the output filter capacitors on this output ground plane. the gnd connection of the adp1829 should be connected to this output ground at the output filter capacitors. 7. generally, be sure that all traces are sized according to the current to be handled as well as their sensitivity in the circuit. standard pcb layout guidelines mainly address heating effects of current in a copper conductor. while these are completely valid, they do not fully cover other concerns such as stray inductance or dc voltage drop. any dc voltage differential in connections between adp1829 gnd and the converter power output ground can cause a significant output voltage error, as it affects converter output voltage according to the ratio with the 600 mv feedback reference. for example, a 6 mv offset between ground on the adp1829 and the converter power output causes a 1% error in the converter output voltage. 8. the csp package has an exposed die paddle on the bottom that efficiently conducts heat to the pcb. adding thermal vias to the pcb provides a thermal path to the inner or bottom layers. because the thermal pad is attached to the die substrate, the planes that the thermal pad is connected to must be electrically isolated or connected to gnd.
eval-adp1829 rev. 0 | page 11 of 16 evaluation board schematic and layout c11 100nf c19 1uf 1 2 3 4 5 6 7 8 9 10111213141516 17 18 19 20 21 22 23 24 25 2627 28 2930 31 32 fb1 comp1 trk1 ss1 vreg in ldosd en2 en1 pok1 bst1 dh1 sw1 csl1 pgnd1 dl1 pv dl2 pgnd2 csl2 sw2 dh2 bst2 pok2 ss2 trk2 comp2 fb2 uv2 gnd freq sync u1 adp1829 c17 6800pf c15 1500pf r15 4.7k r11 1k r9 2k c20 100nf r7 100k c9 0.47uf q1 irlr7807z q5 irfr3709z r3 1.5k l1 2.2uh c1 180uf 20v c21 1uf c12 100nf c10 0.47uf r4 1.5k q2 irlr7807z q8 irfr3709z c2 180uf 20v c22 1uf l2 2.2uh r8 100k c16 820pf c18 4700pf r16 10k r12 2k r18 2k j2 j3 j4 vin 5.5v to 18v vreg gnd sync pok2 vout2 = 1.2v gnd vout1 = 1.8v gnd ss2 ss1 q6 irfr3709z q7 irfr3709z r10 0ohm c14 5600pf r14 392 r6 0ohm r2 0ohm r5 0ohm r1 0ohm r23 100k r17 100k r19 100k r21 50 r20 open r22 open r24 100k trk1 600khz 300khz on on off off off on r13 200 c13 10nf r26 100k fb1 d1 d2 specifications: vin = 5.5v to 18v vout1 = 1.8v @ 15a vout2 = 1.2v @ 15a f sw = 300khz. j1 default. j1 to select between 300khz and 600khz j1 r25 100k fb2 c3 1200uf 6.3v c5 1200uf 6.3v c24 1200uf 6.3v c7 10uf 6.3v c29 not fitted c30 not fitted c31 not fitted c32 not fitted c4 820uf 2.5v c6 820uf 2.5v c23 not fitted c8 10uf 6.3v c25 not fitted c26 not fitted c27 not fitted c28 not fitted trk2 sw2 bst1 pok1 dh1 sw1 dl1 06808-001 figure 16. adp1829 evaluation board schematic, f sw = 300 khz
eval-adp1829 rev. 0 | page 12 of 16 06808-016 figure 17. silk screen layer 06808-017 figure 18. inner layer 1 06808-018 figure 19. top and bottom layers 06808-019 figure 20. inner layer 2 table 1. jumper description jumper description function j1 frequency selection vreg: f sw = 600 khz gnd: f sw = 300 khz j2 ldo shunt down or enable vreg: ldo shunt down gnd: ldo enable j3 channel 1 enable or disable vin: channel 1 enable gnd: channel 1 disable j4 channel 2 enable or disable vin: channel 2 enable gnd: channel 2 disable
eval-adp1829 rev. 0 | page 13 of 16 ordering information bill of materials table 2. item description manufacturer part no. designator qty. 1 capacitor, os-con, 180 f, 20 v sanyo 20sp180m c1, c2 2 2 capacitor, polymer aluminum, 820 f, 2.5 v united chemi-con apsa2r5ell821mhb5s mouser: 661-psa2.5vb820m c4, c6 2 3 capacitor, aluminum electrolytic, 1200 f, 6.3 v rubycon 6.3 zlg1200m 1016 c3, c5, c24 3 4 capacitor, ceramic, 10 f, 6.3 v, x5r, 0805 murata grm21br60j106k c7, c8 2 5 capacitor, ceramic, 0.47 f, 10 v, x5r, 0603 taiyo yuden murata lmk107bj474ma-t grm188r61a474ka61 c9, c10 2 6 capacitor, ceramic, 0.1 f, 10 v, x7r, 0603 vishay vj0603y104mxq c11, c12 2 7 capacitor, ceramic, 10 nf, 50 v, npo, 0603 vishay vj0603y123kxxa c13 1 8 capacitor, ceramic, 5600 pf, 50 v, npo, 0603 vishay vj0603y562 kxxa c14 1 9 capacitor, ceramic, 1500 pf, 50 v, npo, 0603 vishay vj0603y152 kxxa c15 1 10 capacitor, ceramic, 820 pf, 50 v, npo, 0603 vishay vj0603y821 kxxa c16 1 11 capacitor, ceramic, 6800 pf, 10 v, npo, 0603 vishay vj0603y822 kxxa c17 1 12 capacitor, ceramic, 4700 pf, 10 v, npo, 0603 vishay vj0603y472 kxxa c18 1 13 capacitor, ceramic, 1.0 f, 10 v, x5r, 0603 taiyo yuden murata lmk107bj105mk-t grm185r61a105ke36 c19 1 14 capacitor, ceramic, 0.1 f, 50 v, y5v, 0603 taiyo yuden umk107f104za-t c20 1 15 capacitor, ceramic, 1.0 f, 25 v, x5r, 0805 taiyo yuden murata tmk212bj105kg-t grm21br61e105ka99 c21, c22 2 16 capacitor, ceramic not used c 23, c25, c26, c27, c28, c29, c30, c31, c32 9 17 resistor, 0 , 1/10 w, 1%, 0603 vishay crcw06030r00f r1, r2, r5, r6, r10 5 18 resistor, 1.5 k, 1/10 w, 1%, 0603 vishay crcw06031501f r3, r4 2 19 resistor, 100 k, 1/10 w, 1%, 0603 vishay crcw06031003f r7, r8, r17, r19, r23, r24, r25, r26 8 20 resistor, 2.0 k, 1/10 w, 1%, 0603 vishay crcw06032001f r9, r12, r18 3 21 resistor, 1.0 k, 1/10 w, 1%, 0603 vishay crcw06031001f r11 1 22 resistor, 100 k, 1/10 w, 1%, 0603 not used r20, r22 2 23 resistor, 4.75 k, 1/10 w, 1%, 0603 vishay crcw06034751f r15 1 24 resistor, 10 k, 1/10 w, 1%, 0603 vishay crcw06031002f r16 1 25 resistor, 200 , 1/10 w, 1%, 0603 vishay crcw06032000f r13 1 26 resistor, 392 , 1/10 w, 1%, 0603 vishay crcw06032920f r14 1 27 resistor, 49.9 , 1/4 w, 1%, 1206 vishay crcw120649r9f r21 1 28 inductor, 2.2 h, 15 a, 4.5 m dcr toko fda1254-2r2m=p3 l1, l2 2 29 diode, switching, 250 ma, 75 v, sot-23 central semi cmpd4448 d1, d2 2 30 transistor, n mosfet, 30 a, d-pak, 18 m ir irlr7807z q1, q2 2 31 transistor, n mosfet, 60 a, d-pak, 8 m ir irfr3709z q5, q6, q7, q8 4 32 ic, dual interleaved step-down controller with tracking analog devices adp1829 u1 1 33 jumper, 0.1 spacing any j1, j2, j3, j4 4 34 test points any vreg, trk1, trk2, pok1, pok2, fb1, fb2, ss1, ss2, bst1, sw1, sw2, dh1, dl1 14 35 terminal vin, gnd, vout1, gnd, vout2, gnd 6 36 bnc sync 1
eval-adp1829 rev. 0 | page 14 of 16 ordering guide model package description adp1829-evalz 1 evaluation board 1 z = rohs compliant part. esd caution
eval-adp1829 rev. 0 | page 15 of 16 notes
eval-adp1829 rev. 0 | page 16 of 16 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. eb068 08-0-7/07(0)

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